Foundations of parallelism in computer architecture. This course concentrates on the quantitative principles of computer architecture, instruction set and addressing design, instruction-level parallelism (ILP), compiler considerations for parallelism, cache and memory design, multiprocessor (including multi-core processors) and thread-level parallelism (TLP). A constant theme is how the hardware can achieve greater efficiency by exploiting various types of parallelism. Prerequisite: CMPS 3240 Knowledge of a low-level (assembly) language
Basics of digital logic (e.g. adder, ALU, registers, etc.)
Basics of caches and memory design, including virtual memory
Knowledge of the functional organization of computer architecture 4 semester units. 3 units lecture (150 minutes), 1 unit lab (150 minutes). Selected elective for CS Computer Architecture: A Quantitative Approach, 4th edition, John Hennessy and David Patterson, ISBN 0-12-370490-1. None Melissa Danforth, Marc Thomas This course covers the following ACM/IEEE CS2013 (Computer Science) Body of Knowledge student learning outcomes:

AR/Multiprocessing and Alternative Architectures
AR/Performance Enhancements
PD/Parallel Architecture
SF/Quantitative Evaluation

The course maps to the following performance indicators for Computer Science (CAC/ABET):

3a. An ability to apply knowledge of computing and mathematics appropriate to the discipline.

Laboratory/homework assignments and questions on the midterms and final require direct applications of the mathematical theory of algorithms pertinent to computer science.

3c. An ability to design, implement and evaluate a computer-based system, process, component, or program to meet desired needs.

Embedded questions on midterms and final require direct applications of the principles of design under constraints.

3i. An ability to use current techniques, skills, and tools necessary for computing practice.

Laboratory use of the SDE and the assignments made will address this outcome.

Week	Chapter(s)	Topics
1	Chapter 1	Introduction to basic quantitative principles of processor design, Performance
2	Chapter 1 and Appendix B	Instruction set architecture and addressing design
3	Chapter 5 and Appendix C	Introduction to caches and virtual memory
4	Appendix A	Pipelining: Basic concepts
5	Appendix A	Pipelineing: Intermediate concepts, floating point support
6	Chapter 2	Concepts and challenges, Branch prediction
7	Chapter 2	Dynamic scheduling, Reservation stations, Register renaming
8	Chapter 2	Hardware-based speculation
9	Chapter 2	Multiple fetch and multiple issue
10	Chapters 2 and 3	Limitations on ILP, Case study
11	Chapter 2	Compiler design to exploit ILP
12	Chapter 4	Thread-level parallelism and the associated cache-coherancy and virtual memory problems
13 to 15	Chapters 4 and 5	Memory hierarchy: coherency, synchronization, virtual memory

Not applicable to this course. Melissa Danforth on 31 July 2014 Approved by CEE/CS Department on [date]
Effective Fall 2016