CMPS-2240 Homework #6 : Arithmetic Operations & Overflow

Questions taken from these tutorials:


Do this homework in a file.
Create a text file on Odin named 2240/6/a6.txt
When you finish this assignment, rename your file to: hw6.txt
In your text file, choose 3 questions that you think are important.
Briefly talk about what you learned from each question.


Use as needed:

1. What happens when you perform addition on these 8-bit binary numbers if a register can only hold 1 byte (8 bits)?
          1010 1011
        + 0101 0101
          ---------

2. What happens if you get overflow with the following instruction:
   addu  $9, $8, $7

3. What range of signed integers can be represented with 32-bits using two's complement for negative values?

4. What is the size of the operands in the addu operation? Can one of the operands for ori be a negative number?
        ori      $8, $0, 0xAB       
        ori      $9, $0, 0x01      
        addu     $10,$9, $8    

5. Assume register $8 has been loaded with +94 as shown below. What two instructions will give you the two's complement of 94 (i.e., -94)? To produce the two's complement you need to flip (reflect) the bits and then add 1 to the result.
        ori $8, $0, 94

6. What is in $a0 after this code executes?
        ori      $8, $0,  82       
        nor      $8, $8,  $0       
        ori      $9, $0,   1      
        addu     $8, $8,  $9    
        ori      $7, $0,  82   
        addu     $a0, $7, $8  

7. How do addu and addiu differ? Can the operand to addiu be negative? In general why use an immediate instruction?

8. What is in register $9 after this code executes?
        ori      $8, $0, 12     
        sll      $9, $8,  2      
        addu     $9, $9, $8      
        addiu    $9, $9,-15

9. Can you write the same 4 instructions in question #8 with fewer registers?

10. Show that if you multiply one 32-bit unsigned integer in binary by another 32-bit unsigned integer in binary, the binary representation of the product will never be longer than 64 bits.

11. Explain the three multiplication instructions shown below.
         MUL   rd, rs, rt
         MULT  rs, rt
         MULTU rs, rt

12. The multiply unit of MIPS contains a 64-bit accumulator that is divided into two 32-bit registers called Hi and Lo. (These two registers are not general purpose and cannot be accessed directly.) When two 32-bit operands are multiplied, the accumulator holds the result. What is in Hi and what is in Lo?

13. Give one example of two operands for a MULTU instruction that will produce a 0000...0001 in register Hi and all zeros in Lo.

14. What are the significant bits in this unsigned binary number? I.e., which of the 32 bits are significant to computing the value of the number? Assume the least significant bit is the zero-th bit and the most significant bit is the 31st bit.
        0000 0000 0000 0001 0101 0110 1101 1110

15. What are the significant bits in this signed two's complement number? The significant bits are those that would alter the value of the number if omitted. Assume bits are labeled starting at zero from right to left.
        1111 1111 1111 1100 1010 1001 0010 0010

16. What do these instructions do?
       mfhi  $8 
       mflo  $9  

17. What is in $9 after this code execute? q17.s
        ori      $8, $0, 12       
        ori      $9, $0,  5     
        mult     $9, $8         
        mflo     $9             
        addiu    $9, $9,-74

18. Integer division results in a quotient and a remainder. The MIPS div instruction uses the hi and lo registers to hold these values. Where does the quotient go and where does the remainder go?

19. The hi register of this div operation holds what integer operation?
        div rs, rt   # lo holds rs div rt and hi holds what?

20. What is in $10 and what is in $11 after executing this code? q20.s
        ori    $8,   $0,  8     
        ori    $9,   $0, 36  
        addu   $10,  $9, $8  
        subu   $11,  $9, $8    
        div    $10,  $11       
        mflo   $10        
        mfhi   $11

21. What is the difference between a shift right arithmetic (sra) and a shift right logical (srl)? q21.s

22. Do any of the multiplication instructions below trap for overflow? sample code
         MUL   rd, rs, rt
         MULT  rs, rt
         MULTU rs, rt