Lab 7 - Multicycle Datapath

The purpose of this lab is to trace instructions as they pass through the multicycle datapath.

Trace the following assembly program as it travels through the multicycle datapath. For each cycle of each instruction, state the value of the control lines and the value that will be stored in the multicycle registers (PC, IR, MDR, A, B, ALUOut) at the end of that cycle.

Assembly program: 

Memory Address    Label   Instruction
==============    =====   ====================
4000              Loop:   beq $s0, $zero, Exit   # imm = 6, offset to Exit
4004                      add $t0, $s0, $s2      # compute read address
4008                      add $t1, $s0, $s3      # compute write address
4012                      lw $t2, 0($t0)         # read data
4016                      sw $t2, 0($t1)         # write data
4020                      sub $s0, $s0, $s1      # subtract offset
4024                      j Loop                 # imm = 1000 which is 4000/4
4028              Exit:
Assume that the data memory currently looks like the following:

NOTE: There was a typo with the addresses in the 7000 range. See corrected version below. 

Memory Address    Value
==============    =====
7080 7980         0
7084 7984         0
7088 7988         0
7092 7992         0
7096 7996         0
8000              134
8004              82
8008              981
8012              10375
8016              8923
8020              0
8024              0
8028              0
8032              0
8036              0
The initial register values are as follows. Assume the initial value is 0 if the register value is not listed.

NOTE: There was a typo with the addresses in the 7000 range. See corrected version below. 

Register          Value
========          =====
PC                4000
s0                4
s1                -44
s2                7096 7996
s3                8016
For example, the first cycle of the beq $s0, $zero, Exit instruction is the instruction fetch. The values of the control lines for instruction fetch are MemRead, IorD = 0, IRWrite, ALUSrcA = 0, ALUSrcB = 01, ALUOp = 00, PCSource = 00 and PCWrite. The values of each of the registers at the end of instruction fetch are PC = 4004 (PC + 4), IR = 0001 0010 0000 0000 0000 0000 0000 0110 (opcode = 000100 (beq), rs = 10000 (s0), rt = 00000 (zero), imm = 0000 0000 0000 0110 (6, the offset to Exit from the next instruction)), MDR = 0001 0010 0000 0000 0000 0000 0000 0110 (the data line out of memory splits to both IR and MDR), A = 0, B = 0, ALUOut = 4004 (PC + 4).

A few notes

Remember that the registers are not written until the end of the cycle. During the cycle, the PC, IR, etc registers contain whatever values were written into the registers at the end of the previous cycle. Assume for the first cycle of the first instruction that all the registers except PC are 0. PC is 4000 as given in the above table.

The registers are always read on every cycle, which means A and B are written every cycle. What is stored in A and B depends on the rs and rt fields in the IR register. For the above example, since it was the first instruction, IR was 0, so rs and rt were also 0, which reads the values 0 out of the register file. In subsequent instructions, rs and rt will depend on the value in IR, so A and B will likely have some other value than 0 unless rs or rt are reading a register that has stored the value 0.

ALUOut always has the results of the ALU even if it is not used in the next cycle. Thus in the above example, ALUOut is also PC + 4.

MDR will have 0 if the cycle does not set the MemRead control line, the instruction if MemRead is set and IorD is 0 or the data read from memory if MemRead is set and IorD is 1.

Additional Practice

Tracing the loop for the above value of s0 is sufficient for completing this assignment. For more practice, try the code when the loop has more iterations such as starting with s0 = 8 or s0 = 16.