Homework 5 - Chapter 6

1. (4pts) The performance of the pipeline is affected by the time it takes to access memory, since the length of each stage is constrained by this time. Discuss how data hazard resolution (both forwarding and stalling) would be affected if the memory access stage were split into two stages. In other words, our pipeline would now be IF ID EX MEM1 MEM2 WB. Describe the new forwarding logic and hazard detection logic that would be needed.
2. (6pts) The following code is being executed through the pipelined datapath from Figure 6.36, which has the implementation of the hazard detection unit and the forwarding unit to resolve data hazards.

          lw  $t4, 100($t2)
          sub $t6, $t4, $t3
          add $t2, $t3, $t5
       

   Do NOT reorder the code to answer this question.
   1. Draw a diagram (similar to the ones in the solution for #7 in HW4) that shows how these instructions would be pipelined, including all stalls.
   2. Show how the hazard detection unit would detect that a load word instruction is causing the data hazard (i.e. indicate what logic it would use to see that a stall is needed). Show what control lines it would set to initiate the stall.
   3. Show how the forwarding unit would detect (i.e. what logic would it use to see there was a hazard) and resolve (i.e. what control lines would it set) the data hazard in the EX stage for the subtraction command.
3. (4pts) The book describes a method to reduce the delay caused by branch decisions by moving the branch comparison and branch target calculation up to the ID stage. One issue with this method is data hazards caused by previous commands.
   1. For the following code, would a stall still be needed to deal with the data hazards? Justify your answer by explaining why a stall is needed or why no stall is needed.

              Loop:  lw  $t1, 0($s0)
                     add $v0, $v0, $t1
                     add $s0, $s0, $s2
                     slt $t0, $s0, $s1
                     beq $t0, $s3, Loop
              

   2. Write the logic to detect these data hazards. Use the logic from the forwarding unit as a guide. Your algorithm should check the values in the storage register of the previous instruction to see if it generates a result that the branch will need to use when comparing the two registers.
4. (6pts) Assume that you have a program with five branch instructions. You have profiled the branch behavior and determined each branch behaves as follows (T=taken, N=not taken):
   • Branch 1: T-T-T
   • Branch 2: N-N-N-N
   • Branch 3: T-N-T-N-T-N
   • Branch 4: T-T-T-N-T
   • Branch 5: T-T-N-T-T-N-T
   For the following branch predicition schemes, state how often the prediction would be correct and how often it would be wrong.
   1. Assume branch always taken
   2. Assume branch not taken
   3. 1-bit predictor initialized to predict taken (each branch has its own predictor)
   4. 2-bit predictor initialized to weakly predict taken (each branch has its own predictor)