Homework 4 - Chapter 4

NOTE:The last day to turn this assignment in late is Sunday February 24, 2013 at midnight so the solutions can be posted on Monday February 25th to study before Midterm 2.

1. (2 pts) What is a data hazard in the pipelined datapath? What is a control hazard in the pipelined datapath? How can each hazard be handled?
2. (2 pts) The performance of the pipeline is affected by the time it takes to access memory, since the length of each stage is constrained by this time. Discuss how data hazard resolution (both forwarding and stalling) would be affected if the memory access stage were split into two stages. In other words, our pipeline would now be IF ID EX MEM1 MEM2 WB. Describe the new forwarding logic and hazard detection logic that would be needed.
3. (4 pts) In the following MIPS assembly code, identify all the hazards that are present. Show where nop(s) would have to be inserted to deal with the hazard(s), assuming that data forwarding is available and that branch decisions are made in the EX stage.

       Loop: beq  $t5, $a1, Exit      # if t5 == a1, exit loop
             lw   $t0, 0($a0)         # Load fib(n-2)
             lw   $t1, 4($a0)         # Load fib(n-1)
             add  $t2, $t0, $t1       # Calculate fib(n)
             sw   $t2, 8($a0)         # Store fib(n)
             add  $a0, $a0, $s1       # s1 contains 4
             add  $t5, $t5, $s2       # s1 contains 1
             j    Loop
       Exit:
       

4. (2 pts) Show how to reorder the instructions from the previous question to minimize the number of stalls due to data hazards.
5. (6pts) The following code is being executed through the pipelined datapath from Figure 4.60, which has the implementation of the hazard detection unit and the forwarding unit to resolve data hazards.

          lw  $t4, 100($t2)
          sub $t6, $t4, $t3
          add $t2, $t3, $t5
       

   Do NOT reorder the code to answer this question.
   1. Draw a diagram that shows how these instructions would be pipelined, including all stalls (similar to Figure 4.59).
   2. Show how the hazard detection unit would detect that the load word instruction is causing the data hazard (i.e. indicate what logic it would use to see that a stall is needed). Show what control lines it would set to initiate the stall.
   3. Show how the forwarding unit would detect (i.e. what logic would it use to see there was a hazard) and resolve (i.e. what control lines would it set) the data hazard in the EX stage for the subtraction command.
6. (4pts) The book describes a method to reduce the delay caused by branch decisions by moving the branch comparison and branch target calculation up to the ID stage. One issue with this method is data hazards caused by previous commands, e.g. the values being compared by the branch may not be available in the ID stage if they are still being calculated in other portions of the pipeline.
   1. For the following code, would a stall still be needed to deal with the data hazards? Justify your answer by explaining why a stall is needed or why no stall is needed.

              Loop:  lw  $t1, 0($s0)
                     add $v0, $v0, $t1
                     add $s0, $s0, $s2
                     slt $t0, $s0, $s1
                     beq $t0, $s3, Loop
              

   2. Write the logic to detect these data hazards. Use the logic from the forwarding unit as a guide. Your algorithm should check the values in the storage register of the previous instruction to see if it generates a result that the branch will need to use when comparing the two registers.