Homework 5 - Chapters 4 and 6

1. (6 pts) Assume that you have a program with five branch instructions. You have profiled the branch behavior and determined each branch behaves as follows (T=taken, N=not taken):
   • Branch 1: T-T-T
   • Branch 2: N-N-N-N
   • Branch 3: T-N-T-N-T-N
   • Branch 4: T-T-T-N-T
   • Branch 5: T-T-N-T-T-N-T
   Pretend that you are now starting the program again from the beginning, but that the branches will behave exactly the same. For the following branch predicition schemes, state how often the prediction would be correct and how often it would be wrong for each one of the branches.
   1. Assume branch taken
   2. Assume branch not taken
   3. 2-bit predictor initialized to weakly predict taken (each branch has its own predictor)
2. (2 pts) Describe the challenges that are presented when doing exception handling in a pipelined datapath.
3. (2 pts) What is the difference between precise interrupts and imprecise interrupts?
4. (4 pts) For the following instructions, state what kind(s) of exceptions may be generated by the instruction and which pipeline stage(s) each potential exception would be detected in (see page 433 for a list of exceptions):
   1. lw $t3, 4($t1)
   2. add $t5, $t2, $a1
5. (2 pts) What is one motivation for doing I/O interrupts instead of I/O polling?
6. (2 pts) Compare and contrast synchronous and asynchronous I/O busses. State devices that would be well-suited to each and devices that would be poorly suited to each.
7. (2 pts) How are cache coherency issues addressed when using Direct Memory Access (DMA) for a device?